Design Considerations of SOPC-Based H.264/AVC Systems

The primary advantage of the H.264 video compression technique is the ability to provide good video quality at substantially lower bit rates compared with other video compression methods. This is due to the use of variable block sizes, multiple reference frames, and the consideration of Rate-Distortion Optimization (RDO). However, these features come with the price of added complexity due to the introduction of Motion Estimation (ME) and Mode Decision (MD) in the design of H.264. This paper aims to compile a collection of research to aid designers in applying the H.264 technology to a variety of different applications. These research topics include complexity reduction, vector edge detection, and added efficiency in H.264 architectures. Complexity is reduced by a cost-effective coding algorithm for removing ME redundancy in System-on-aProgrammable Chip (SOPC)-based embedded systems. Improvement in vector edge detection is accomplished by a cost-effective method which stores all vector information within a frame and places said information in the Laplacian of Gaussian Operator. Lastly, an efficient architectural design is reviewed in analyzing the bandwidth of each component in an H.264 design. The entire system bandwidth is decomposed into several modules with predictable coefficients, thereby aiding designers in understanding the real cost of each hardware component.